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Features
* Utilizes the AVR(R) Enhanced RISC Architecture * 121 Powerful Instructions - Most Single Clock Cycle Execution * 128K bytes of In-System Reprogrammable Flash ATMEGA103/L
64K bytes of In-System Reprogrammable Flash ATmega603/L - SPI Interface for In-System Programming - Endurance: 1,000 Write/Erase Cycles 4K bytes EEPROM ATMEGA103/L 2K bytes of EEPROM ATmega603/L - Endurance: 100,000 Write/Erase Cycles 4K bytes Internal SRAM 32 x 8 General Purpose Working Registers + Peripheral Control Registers 32 Programmable I/O Lines, 8 Output Lines, 8 Input Lines Programmable Serial UART + SPI Serial Interface VCC Supply - 2.7 - 3.6V ATmega603L/ATMEGA103L - 4.0 - 5.5V ATmega603/ATMEGA103 Fully Static Operation - 0 - 6 MHz ATmega603/ATMEGA103 - 0 - 4 MHz ATmega603L/ATMEGA103L Up to 6 MIPS Throughput at 6 MHz RTC with Separate Oscillator Two 8-Bit Timer/Counters with Separate Prescaler and PWM One 16-Bit Timer/Counter with Separate Prescaler, Compare, Capture Modes and Dual 8-, 9- or 10-Bit PWM Programmable Watchdog Timer with On-Chip Oscillator On-Chip Analog Comparator 8-Channel, 10-Bit ADC Low Power Idle, Power Save and Power Down Modes Software Selectable Clock Frequency Programming Lock for Software Security
* * * * * * * * * * * * * * * * *
8-Bit Microcontroller with 64K/128K Bytes In-System Programmable Flash ATmega603 ATmega603L ATMEGA103 ATMEGA103L Preliminary ATMEGA103/L ATMEGA103/L
Pin Configuration
TQFP
Rev. 0945BS-09/98
Note:
This is a summary document. For the complete 92 page document, please visit our web site at 1 www.atmel.com or e-mail at literature@atmel.com and request literature #0945B.
Block Diagram
Figure 1. The ATmega603/103 Block Diagram
PF0 - PF7 PA0 - PA7 PC0 - PC7
VCC GND PORTF BUFFERS AVCC DATA REGISTER PORTA DATA DIR. REG. PORTA DATA REGISTER PORTC 8-BIT DATA BUS PORTA DRIVER/BUFFERS PORTC DRIVERS
ANALOG MUX
ADC
AGND AREF INTERNAL OSCILLATOR OSCILLATOR
XTAL1
XTAL1 PROGRAM COUNTER STACK POINTER WATCHDOG TIMER TOSC2
OSCILLATOR
PROGRAM FLASH
SRAM
MCU CONTROL REGISTER
TIMING AND CONTROL
TOSC1
INSTRUCTION REGISTER
GENERAL PURPOSE REGISTERS
X Y Z
TIMER/ COUNTERS
RESET ALE WR RD
INSTRUCTION DECODER
INTERRUPT UNIT
CONTROL LINES
ALU
EEPROM
STATUS REGISTER
PROGRAMMING LOGIC
PEN
SPI
UART
ANALOG COMPARATOR
DATA REGISTER PORTE
DATA DIR. REG. PORTE
DATA REGISTER PORTB
DATA DIR. REG. PORTB
DATA REGISTER PORTD
DATA DIR. REG. PORTD
+ -
VCC PORTE DRIVER/BUFFERS PORTB DRIVER/BUFFERS PORTD DRIVER/BUFFERS GND
PE0 - PE7
PB0 - PB7
PD0 - PD7
Description
The ATmega603/103 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega603/103 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. The AVR core is based on an enhanced RISC architecture that combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture 2 is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega603/103 provides the following features: 64K/128K bytes of In-system Programmable Flash, 2K/4K bytes EEPROM, 4K bytes SRAM, 32 general purpose I/O lines, 8 Input lines, 8 Output lines, 32 general purpose working registers, 4 flexible timer/counters with compare modes and PWM, UART, programmable Watchdog Timer with internal oscillator, an SPI serial port and three software selectable power saving modes. The Idle Mode stops the CPU while allowing the SRAM, timer/counters, SPI port and interrupt system to continue functioning. The Power
ATmega603(L) and ATMEGA103(L)
ATmega603(L) and ATMEGA103(L)
Down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Power Save mode, the timer oscillator continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The device is manufactured using Atmel's high-density non-volatile memory technology. The on-chip ISP Flash allows the program memory to be reprogrammed in-system through a serial interface or by a conventional nonvolatile memory programmer. By combining an 8-bit RISC CPU with a large array of ISP Flash on a monolithic chip, the Atmel ATmega603/103 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega603/103 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. Port A serves as Multiplexed Address/Data bus when using external SRAM. Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O pins with internal pull-up resistors. The Port B output buffers can sink 20 mA. As inputs, Port B pins that are externally pulled low, will source current if the pull-up resistors are activated. Port B also serves the functions of various special features. Port C (PC7..PC0) Port C is an 8-bit Output port. The Port C output buffers can sink 20 mA. Port C also serves as Address output when using external SRAM. Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. Port D also serves the functions of various special features. Port E (PE7..PE0) Port E is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port E output buffers can sink 20 mA. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. Port E also serves the functions of various special features. Port F (PF7..PF0) Port F is an 8-bit Input port. Port F also serves as the analog inputs for the ADC. RESET input. A low on this pin for two machine cycles while the oscillator is running resets the device. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2 Output from the inverting oscillator amplifier TOSC1 Input to the inverting Timer/Counter oscillator amplifier TOSC2 Output from the inverting Timer/Counter oscillator amplifier WR External SRAM Write Strobe. RD External SRAM Read Strobe. ALE ALE is the Address Latch Enable used when the External Memory is enabled. The ALE strobe is used to latch the low-order address (8 bits) into an address latch during the
Comparison Between ATmega 603 and ATmega 103
The ATmega603 has 64K bytes of In-System Programmable Flash, 2K bytes of EEPROM, and 4K bytes of internal SRAM. The ATmega603 does not have the ELPM instruction. The ATMEGA103 has 128K bytes of In-System Programmable Flash, 4K bytes of EEPROM, and 4K bytes of internal SRAM. The ATMEGA103 has the ELPM instruction, necessary to reach the upper half of the Flash memory for constant table lookup. Table 1 summarizes the different memory sizes for the two devices. Table 1. Memory Size Summary
Part ATmega603 ATMEGA103 Flash 64K bytes 128K bytes EEPROM 2K bytes 4K bytes SRAM 4K bytes 4K bytes
Pin Descriptions
VCC Supply voltage GND Ground Port A (PA7..PA0) Port A is an 8-bit bi-directional I/O port. Port pins can provide internal pull-up resistors (selected for each bit). The Port A output buffers can sink 20 mA and can drive LED displays directly. When pins PA0 to PA7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated.
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first access cycle, and the AD0-7 pins are used for data during the second access cycle. AVCC This is the supply voltage to the A/D Converter. It should be externally connected to V CC via a low-pass filter. See page 53 for details on operation of the ADC. AREF This is the analog reference input for the ADC converter. For ADC operations, a voltage in the range AGND to AVCC must be applied to this pin. AGND If the board has a separate analog ground plane, this pin should be connected to this ground plane. Otherwise, connect to GND. PEN This is a programming enable pin for the low-voltage serial programming mode. By holding this pin low during a poweron reset, the device will enter the serial programming mode.
Figure 3. External Clock Drive Configuration
NC XTAL2
EXTERNAL OSCILLATOR SIGNAL
XTAL1
GND
ATmega603/103 Architectural Overview
The fast-access register file contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This means that during one single clock cycle, one ALU (Arithmetic Logic Unit) operation is executed. Two operands are output from the register file, the operation is executed, and the result is stored back in the register file in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing enabling efficient address calculations. One of the three address pointers is also used as the address pointer for the constant table look up function. These added function registers are the 16-bit X-register, Y-register and Z-register. The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register operations are also executed in the ALU. Figure 4 shows the ATmega603/103 AVR Enhanced RISC microcontroller architecture. In addition to the register operation, the conventional memory addressing modes can be used on the register file as well. This is enabled by the fact that the register file is assigned the 32 lowermost Data Space addresses, allowing them to be accessed as though they were ordinary memory locations. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, Timer/Counters, A/D-converters, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the register file, $20 - $5F.
Crystal Oscillator
XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 2. Either a quartz crystal or a ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 3. For the Timer Oscillator pins, OSC1 and OSC2, the crystal is connected directly between the pins. No external capacitors are needed. The oscillator is optimized for use with a 32,768Hz watch crystal. An external clock signal applied to this pin goes through the same amplifier having a bandwidth of 256kHz. The external clock signal should therefore be in the interval 0Hz - 256kHz. Figure 2. Oscillator Connections
C2 XTAL2
C1 XTAL1
GND
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ATmega603(L) and ATMEGA103(L)
ATmega603(L) and ATMEGA103(L)
Figure 4. The ATmega603/103 AVR Enhanced RISC Architecture
AVR ATmega603/103 Architecture
Data Bus 8-bit
32K/64K x 16 Program Memory
Program Counter
Status and Test
Instruction Register
32 x 8 General Purpose Registers Peripherals
Instruction Decoder
IndirectAddressing
DirectAddressing
ALU
Control Lines
4K x 8 Data SRAM
2K/4K x 8 EEPROM
The AVR uses a Harvard architecture concept - with separate memories and buses for program and data. The program memory is executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is in-system programmable Flash memory. With a few exceptions, AVR instructions have a single 16-bit word format, meaning that every program memory address contains a single 16-bit instruction. During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is effectively allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are executed). The 16-bit stack pointer SP is read/write accessible in the I/O space.
The 4000 bytes data SRAM can be easily accessed through the five different addressing modes supported in the AVR architecture. A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status register. All the different interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the program memory. The different interrupts have priority in accordance with their interrupt vector position. The lower the interrupt vector address, the higher the priority. The memory spaces in the AVR architecture are all linear and regular memory maps.
The General Purpose Register File
Figure 5 shows the structure of the 32 general purpose working registers in the CPU.
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ATmega603/103 Register Summary
Address $3F ($5F) $3E ($5E) $3D ($5D) $3C ($5C) $3B ($5B) $3A ($5A) $39 ($59) $38 ($58) $37 ($57) $36 ($56) $35 ($55) $34 ($54) $33 ($53) $32 ($52) $31 ($51) $30 ($50) $2F ($4F) $2E ($4E) $2D ($4D) $2C ($4C) $2B ($4B) $2A ($4A) $29 ($49) $28 ($48) $27 ($47) $26 ($46) $25 ($45) $24 ($44) $23 ($43) $21 ($47) $1F ($3F) $1E ($3E) $1D ($3D) $1C ($3C) $1B ($3B) $1A ($3A) $19 ($39) $18 ($38) $17 ($37) $16 ($36) $15 ($35) $12 ($32) $11 ($31) $10 ($30) $0F ($2F) $0E ($2E) $0D ($2D) $0C ($2C) $0B ($2B) $0A ($2A) $09 ($29) $08 ($28) $07 ($27) $06 ($26) $05 ($25) $04 ($24) $03 ($23) $02 ($22) $01 ($21) $00 ($20) Name SREG SPH SPL XDIV RAMPZ EICR EIMSK EIFR TIMSK TIFR MCUCR MCUSR TCCR0 TCNT0 OCR0 ASSR TCCR1A TCCR1B TCNT1H TCNT1L OCR1AH OCR1AL OCR1BH OCR1BL ICR1H ICR1L TCCR2 TCNT2 OCR2 WDTCR EEARH EEARL EEDR EECR PORTA DDRA PINA PORTB DDRB PINB PORTC PORTD DDRD PIND SPDR SPSR SPCR UDR USR UCR UBRR ACSR ADMUX ADCSR ADCH ADCL PORTE DDRE PINE PINF Bit7 I SP15 SP7 XDIVEN ISC71 INT7 INTF7 OCIE2 OCF2 SRE Bit6 T SP14 SP6 XDIV6 ISC70 INT6 INTF6 TOIE2 TOV2 SRW PWM0 Bit5 H SP13 SP5 XDIV5 ISC61 INT5 INTF5 TICIE1 ICF1 SE COM01 Bit4 S SP12 SP4 XDIV4 ISC60 INT4 INTF4 OCIE1A OCF1A SM1 COM00 Bit3 V SP11 SP3 XDIV3 ISC51 INT3 OCIE1B OCF1B SM0 CTC0 Bit2 N SP10 SP2 XDIV2 ISC50 INT2 TOIE1 TOV1 CS02 Bit1 Z SP9 SP1 XDIV1 ISC41 INT1 OCIE0 OCF0 EXTRF CS01 Bit0 C SP8 SP0 XDIV0 RAMPZ0 ISC40 INT0 TOIE0 TOV0 PORF CS00 Page page 14 page 14 page 14 page 16 page 15 page 23 page 22 page 22 page 23 page 24 page 15 page 21 page 28 page 30 page 30 COM1B0 AS0 CTC1 TCN0UB CS12 OCR0UB PWM11 CS11 TCR0UB PWM10 CS10 page 32 page 34 page 37 page 36 page 36 page 37 page 37 page 37 page 37 page 37 page 37 COM20 CTC2 CS22 CS21 CS20 page 28 page 30 page 30 WDTOE WDE EEAR11 WDP2 EEAR10 WDP1 EEAR9 WDP0 EEAR8 page 40 page 41 page 41 page 41 PORTA5 DDA5 PINA5 PORTB5 DDB5 PINB5 PORTC5 PORTD5 DDD5 PIND5 DORD UDRE UDRIE ACO ADRF ADC5 PORTE5 DDE5 PINE5 PINF5 PORTA4 DDA4 PINA4 PORTB4 DDB4 PINB4 PORTC4 PORTD4 DDD4 PIND4 MSTR FE RXEN ACI ADIF ADC4 PORTE4 DDE4 PINE4 PINF4 EERIE PORTA3 DDA3 PINA3 PORTB3 DDB3 PINB3 PORTC3 PORTD3 DDD3 PIND3 CPOL OR TXEN ACIE ADIE ADC3 PORTE3 DDE3 PINE3 PINF3 EEMWE PORTA2 DDA2 PINA2 PORTB2 DDB2 PINB2 PORTC2 PORTD2 DDD2 PIND2 CPHA CHR9 ACIC MUX2 ADPS2 ADC2 PORTE2 DDE2 PINE2 PINF2 EEWE PORTA1 DDA1 PINA1 PORTB1 DDB1 PINB1 PORTC1 PORTD1 DDD1 PIND1 SPR1 RXB8 ACIS1 MUX1 ADPS1 ADC9 ADC1 PORTE1 DDE1 PINE1 PINF1 EERE PORTA0 DDA0 PINA0 PORTB0 DDB0 PINB0 PORTC0 PORTD0 DDD0 PIND0 SPR0 TXB8 ACIS0 MUX0 ADPS0 ADC8 ADC0 PORTE0 DDE0 PINE0 PINF0 page 41 page 57 page 57 page 57 page 59 page 59 page 59 page 65 page 66 page 66 page 66 page 46 WCOL SPE TXC TXCIE ABSY ADC6 PORTE6 DDE6 PINE6 PINF6 page 46 page 45 page 49 page 49 page 50 page 51 page 52 page 54 page 54 page 55 page 55 page 69 page 69 page 69 page 73 COM1B1 -
Timer/Counter0 (8 Bit) Timer/Counter0 Output Compare Register COM1A1 ICNC1 COM1A0 ICES1
Timer/Counter1 - Counter Register High Byte Timer/Counter1 - Counter Register Low Byte Timer/Counter1 - Output Compare Register A High Byte Timer/Counter1 - Output Compare Register A Low Byte Timer/Counter1 - Output Compare Register B High Byte Timer/Counter1 - Output Compare Register B Low Byte Timer/Counter1 - Input Capture Register High Byte Timer/Counter1 - Input Capture Register Low Byte PWM2 COM21 Timer/Counter2 (8 Bit) Timer/Counter2 Output Compare Register EEPROM Address Register L EEPROM Data Register PORTA7 DDA7 PINA7 PORTB7 DDB7 PINB7 PORTC7 PORTD7 DDD7 PIND7 SPI Data Register SPIF SPIE RXC RXCIE ACD ADES ADC7 PORTE7 DDE7 PINE7 PINF7 PORTA6 DDA6 PINA6 PORTB6 DDB6 PINB6 PORTC6 PORTD6 DDD6 PIND6
UART I/O Data Register
UART Baud Rate Register
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ATmega603(L) and ATMEGA103(L)
ATmega603(L) and ATMEGA103(L)
ATmega603/103 Instruction Set Summary
Mnemonics Operands Description Operation Rd Rd + Rr Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER RJMP IJMP JMP RCALL ICALL CALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC BRIE BRID Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b Pb , Pb , s, k s, k k k k k k k k k k k k k k k k k k k k k k Rd, Rr Rd, Rr Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd k Add two Registers Add with Carry two Registers Add Immediate to Word Subtract two Registers Subtract Constant from Register Subtract with Carry two Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers One's Complement Two's Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Relative Jump Indirect Jump to (Z) Direct Jump Relative Subroutine Call Indirect Call to (Z) Direct Subroutine Call Subroutine Return Interrupt Return Compare, Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less Than Zero, Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if T Flag Cleared Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared Branch if Interrupt Enabled Branch if Interrupt Disabled Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None None None None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None None None None None None 1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 3 3 3 4 4 4 1/2 1 1 1 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 Rd Rd + Rr + C Rd Rd - Rr Rd Rd - K
Rdh:Rdl Rdh:Rdl + K
Rd Rd - K - C Rd
Rd Rd - Rr - C Rdh:Rdl Rdh:Rdl - K
Rd Rd * K Rd Rd v K
Rd * Rr
Rd Rd v Rr
Rd $FF - Rd Rd Rd v K Rd Rd + 1 Rd Rd - 1 Rd $00 - Rd
Rd Rd Rr
Rd Rd * ($FF - K)
Rd Rd * Rd Rd
Rd Rd Rd $FF
PC PC + k + 1
BRANCH INSTRUCTIONS PC Z PC k
PC Z PC k
PC PC + k + 1
PC STACK Rd - Rr Rd - Rr - C Rd - K
PC STACK if (Rd = Rr) PC PC + 2 or 3
if (Rr(b)=1) PC PC + 2 or 3 if (P(b)=1) PC PC + 2 or 3 if (P(b)=0) PC PC + 2 or 3
if (Rr(b)=0) PC PC + 2 or 3
if (SREG(s) = 1) then PCPC+k + 1 if (SREG(s) = 0) then PCPC+k + 1 if (Z = 1) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1
if (C = 0) then PC PC + k + 1
if (N = 1) then PC PC + k + 1 if (N V= 0) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (N V= 1) then PC PC + k + 1
if (H = 0) then PC PC + k + 1 if (T = 0) then PC PC + k + 1
if (T = 1) then PC PC + k + 1
if (V = 0) then PC PC + k + 1 if ( I = 0) then PC PC + k + 1 if ( I = 1) then PC PC + k + 1
if (V = 1) then PC PC + k + 1
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ATmega603/103 Instruction Set Summary (Continued)
DATA TRANSFER INSTRUCTIONS ELPM() MOV LDI LD LD LD LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM IN OUT PUSH POP SBI CBI LSL LSR ROL ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH NOP SLEEP WDR Rd, P P Rr , Rr Rd P ,b P ,b Rd Rd Rd Rd Rd Rd s s Rr, b Rd, b Rd, Rr Rd, K Rd, X Rd, X+ Rd, - X Rd, Y Rd, Y+ Rd, - Y Rd,Y+q Rd, Z Rd, Z+ Rd, -Z Rd, Z+q Rd, k X, Rr X+, Rr - X, Rr Y, Rr Y+, Rr - Y, Rr Y+q,Rr Z, Rr Z+, Rr -Z, Rr Z+q,Rr k, Rr Extended Load Program Memory Move Between Registers Load Immediate Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Direct to SRAM Load Program Memory In Port Out Port Push Register on Stack Pop Register from Stack Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rotate Right Through Carry Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Twos Complement Overflow. Clear Twos Complement Overflow Set T in SREG Clear T in SREG Set Half Carry Flag in SREG Clear Half Carry Flag in SREG No Operation Sleep Watchdog Reset (see specific descr. for Sleep function) (see specific descr. for WD timer) R0 (Z+RAMPZ) None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H H None None None 3 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 1 1 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 1 Rd Rr
K Rd (X) Rd (X), X X + 1 X X - 1, Rd (X) Rd (Y) Rd (Y), Y Y + 1 Y Y - 1, Rd (Y) Rd (Y + q) Rd (Z) Rd (Z), Z Z+1 Z Z - 1, Rd (Z) Rd (Z + q) Rd (k) (X) Rr (X) Rr, X X + 1 X X - 1, (X) Rr (Y) Rr (Y) Rr, Y Y + 1 Y Y - 1, (Y) Rr (Y + q) Rr (Z) Rr (Z) Rr, Z Z + 1 Z Z - 1, (Z) Rr (Z + q) Rr (k) Rr R0 (Z) Rd P P Rr STACK Rr Rd STACK
Rd I/O(P 1 ,b) Rd(n+1) Rd(n), Rd(0) 0 I/O(P 0 ,b)
BIT AND BIT-TEST INSTRUCTIONS
Rd(n) Rd(n+1), Rd(7) 0 Rd(0)C,Rd(n+1) Rd(n),CRd(7) Rd(7)C,Rd(n) Rd(n+1),CRd(0) Rd(n) Rd(n+1), n=0..6 Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) SREG(s) 1 T Rr(b) C1 N1 C0 SREG(s) 0 Rd(b) T
Z0 I0 I1
Z1
N0
V1 V0 T0 T1
S0
S1
H1 H0
8
ATmega603(L) and ATMEGA103(L)
ATmega603(L) and ATMEGA103(L)
Ordering Information
Speed (MHz) 4 Power Supply 2.7 - 3.6V Ordering Code ATmega603L-4AC ATmega603L-4AI 6 4.0 - 5.5V ATmega603-6AC ATmega603-6AI 4 2.7 - 3.6V ATMEGA103L-4AC ATMEGA103L-4AI 6 4.0 - 5.5V ATMEGA103-6AC ATMEGA103-6AI Package 64A 64A 64A 64A 64A 64A 64A 64A Operation Range Commercial (0C to 70C) Industrial (-40C to 85C) Commercial (0C to 70C) Industrial (-40C to 85C) Commercial (0C to 70C) Industrial (-40C to 85C) Commercial (0C to 70C) Industrial (-40C to 85C)
Package Type 64A 64-Lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)
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Packaging Information
64A, 64-Lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) Dimensions in Millimeters and (Inches)*
16.25(0.640) SQ 15.75(0.620)
PIN 1 ID 0.45(0.018) 0.30(0.012)
0.80(0.031) BSC
14.10(0.555) SQ 13.90(0.547) 0.20(0.008) 0.10(0.004) 0-7 0.75(0.030) 0.45(0.018) 0.15(0.006) 0.05(0.002 )
1.20 (.047) MAX
*Controlling dimension: millimeters
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ATmega603(L) and ATMEGA103(L)

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